This invention relates to computer systems for processing analog and digital data from a multitude of sources, received at a wide range of input data rates and processed at very much higher speed according to readily variable programs.
State-of-the-art process controls, data acquisition, simulation, or training systems require custom data acquisition and control units to process analog and digital data. The data acquisition and control units must be reliable and flexible. The present invention is such a system incorporating an internal data communication technique for custom data acquisition and control equipment that has the following features:
1. A standard internal architecture that can be used for many different applications; PA0 2. Can interface a large number of analog and digital data input and output converters (this capability is referred to herein as "fanout"); PA0 3. Can be expanded easily to accomodate a specific task; PA0 4. Accomodates a mix of relatively high data rate and low data rate input and output data converters; PA0 5. Accepts and processes the input and output data at relatively much higher data rates than the rate that the data is input and output; PA0 6. Can be custom configured for a specific task with minimum design time and expense; PA0 7. Is programmable with software; PA0 8. Has built in an extensive self-test and fault diagnostic capability; and PA0 9. Has built in a data error correcting capability.
In the past, there has been two approaches to data acquisition and control equipment design. According to one of these, custom-designed units are configured to process a defined fixed set of input and output (I/O) signals. Each of these custom equipments is different and has its own custom designed, hard-wired logic which is optimized for one particular application. The shortcomings of this approach are:
It is time-consumsing and expensive, because the equipment must be redesigned for each application; and PA1 The equipment cannot be expanded or re-configured; and PA1 The equipment does not have a standard internal architecture. PA1 Inadequate fanout and expansion capability so they cannot support large systems; PA1 Limited internal self-test capability; PA1 Not easily programmed for different system requirements; PA1 Inadequate high-speed data transfer capability, i.e. the high-speed bus does not have sufficient direct memory access (DMA) data rates and/or it cannot support multiple high-speed simultaneous data transfers; PA1 Cannot handle a mix of modules operating at different data rates; and PA1 There is no provision for data error correcting.
According to another prior approach, equipments are based on bus-oriented, modular design. In general, these equipments feature a series of standardized modules that interface to a defined, standard digital communication bus on which all module-to-module data is transferred. Some equipments are a combination of two or three buses that enable the system to support different types of modules. Typically, one bus handles high data rate processing modules while another handles low date rate processing modules. None of these prior techniques address the total problem and all have serious shortcomings. None provide the features listed above that are included in the applicant's system. The limitations of the prior techniques vary from equipment to equipment and include the following general problems:
It is an object of the present invention to provide a computer system incorporating the above numbered features while avoiding the limitations of prior systems.